The present invention relates to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing integrated circuits having transistors with ultrashallow source/drain extensions.
Currently, deep-submicron complementary metal oxide semiconductor (CMOS) is the primary technology for ultra-large scale integrated (ULSI) devices. Over the last two decades, reduction in the size of CMOS transistors has been a principal focus of the microelectronics industry. However, as the sizes of the various components of the transistor are reduced, operational parameters and performance characteristics can change. Appropriate transistor performance must be maintained as transistor size is decreased.
The ULSI circuit can include CMOS field effect transistors (FETS). The transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and draininduced barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or an ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is doped a second time to form the deeper source and drain regions. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacer.
As transistors disposed on integrated circuits (ICs) become smaller, transistors with shallow and ultra-shallow source/drain extensions have become more difficult to manufacture. For example, smaller transistors should have ultrashallow source and drain extensions with less than 30 nanometer (nm) junction depth. Forming source and drain extensions with junction depths of less than 30 nm is very difficult using conventional fabrication techniques. Conventional ion implantation and diffusion-doping techniques make transistors on the IC susceptible to short-channel effects, which result in a dopant profile tail distribution that extends deep into the substrate. Also, conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because point defects generated in the bulk semiconductor substrate during ion implantation can cause the dopant to more easily diffuse (transient enhanced diffusion, TED). The diffusion often extends the source and drain extension vertically into the bulk semiconductor substrate.
Transistors, such as, metal oxide semiconductor field effect transistors (MOSFETs), are generally either bulk semiconductor-type devices or silicon-on-insulator (SOI)-type devices. Most integrated circuits are fabricated in a CMOS process on a bulk semiconductor substrate.
In bulk semiconductor-type devices, transistors, such as, MOSFETs, are built on the top surface of a bulk substrate. The substrate is doped to form source and drain regions, and a conductive layer is provided between the source and drain regions. The conductive layer operates as a gate for the transistor; the gate controls current in a channel between the source and the drain regions. As transistors become smaller, the body thickness of the transistor (or thickness of depletion layer below the inversion channel) must be scaled down to achieve superior short-channel performance.
Conventional SOI-type devices include an insulative substrate attached to a thin-film semiconductor substrate that contains transistors similar to the MOSFETs described with respect to bulk semiconductor-type devices. The insulative substrate generally includes a buried insulative layer above a lower semiconductor base layer. The transistors on the insulative substrate have superior performance characteristics due to the thin-film nature of the semiconductor substrate and the insulative properties of the buried insulative layer. In a fully depleted (FD) MOSFET, the body thickness is so small that the depletion region has a limited vertical extension, thereby eliminating link effect and lowering hot carrier degradation. The superior performance of SOI devices is manifested in superior short-channel performance (i.e., resistance to process variation in small size transistor), near-ideal subthreshold voltage swing (i.e., good for low off-state current leakage), and high saturation current.
As the physical gate length of MOS transistors shrink to dimensions of 50 nm and below, ultra-thin-body MOSFETs fabricated on very thin SOI substrates provide significant architectural advantages. The body thickness of such devices can be below 200 Angstroms (xc3x85) to overcome the short-channel effects (e.g., threshold voltage roll-off and drain induced barrier lowering) which tend to be severe in devices with small dimensions.
The source region and drain regions of such devices can be raised by selective silicon (SI) epitaxy to make connections to source and drain contacts less difficult. The raised source and drain region provide additional material for contact silicidation processes. However, the raised source and drain region do not necessarily make conventional doping processing for source and drain junctions less challenging especially with respect to transistors with small gate lengths. The spacing between the source and drain regions in devices with gate lengths below 70 nm is extremely narrow (e.g., only 25-30 nm).
According to conventional doping techniques, the dopant implanted into the source and drain region must be activated at temperatures of 900-1100xc2x0 C. for several seconds. The high thermal budget associated with conventional doping techniques can produce significant thermal diffusion which can cause a short between the source and drain region. Shorting between the source and drain region is a particular problem at small gate lengths.
Thus, there is a need for an integrated circuit or electronic device that includes transistors not susceptible to shorts caused by dopant thermal diffusion. Further still, there is a need for an SOI circuit that has transistors with an abrupt lateral dopant gradient. Even further still, there is a need for source and drain regions having dopants activated in a low thermal budget process. Yet further still, there is a need for an SO integrated circuit with transistors having gate lengths of about 50 nm and below.
The present invention relates to a method of manufacturing an integrated circuit including a plurality of transistors. The plurality of transistors include a first transistor having a gate structure disposed on a film. The method includes forming an elevated source region and an elevated drain region on the substrate, amorphizing the elevated source region and the elevated drain region, and providing dopants to the elevated source region and the elevated drain region. The method also includes annealing the elevated source region and the elevated drain region to recrystallize the elevated source region and elevated drain region. The gate structure is between the elevated source region and the elevated drain region.
The present invention further relates to a semiconductor-on-insulator integrated circuit including a transistor. The transistor includes a gate disposed between an elevated source region and an elevated drain region. The elevated drain region and the elevated source region are amorphized, doped, and subjected to a low thermal budget process to crystallize the elevated source and drain region.
The present invention further relates to a method of manufacturing a ULSI circuit on a semiconductor-on-insulator substrate. The substrate includes a gate disposed on a semiconductor film. The method includes selectively depositing a semiconductor film to form a first structure at a first location and a second structure at a second location, providing neutral dopants to the first structure and the second structure, and doping the first structure and the second structure with non-neutral dopants. The gate is between the first location and the second location. The neutral dopants form amorphous regions in the first structure and the second structure.